Expériences professionnelles
Senior manager partner ecosystem
Arteris
Depuis le 01 décembre 2024
Expert, mentor, and keynote speaker
EuroCDP - EU Chips Design Platform
Depuis le 01 avril 2026
Mentor - next-gen computing
Creative Destruction Lab , Paris
Depuis le 01 février 2025
Freelance strategy consultant - strategy mission in semiconductor investment
Freelance - France , Toulouse - CDI (Contrat à Durée Indéterminée)
De Janvier 2024 à Juin 2024
Bridging semiconductor expertise with financial markets to drive strategic investment decisions in a dynamic geopolitical environment:
- Established robust due diligence and risk management frameworks for semiconductor IP investments, aiming at a €230M serviceable market by 2028
- Designed a global expansion strategy with specialized teams across Europe, the USA, and Asia to leverage regional semiconductor ecosystems and deliver localized insights
- Developed a multi-tiered service model, integrating subscription-based monitoring, premium advisory, and specialized technical analysis tailored for institutional investors
Freelance strategy consultant - semiconductor ip market intelligence strategy mission
Freelance - France , Toulouse - CDD (Contrat à Durée Déterminée)
De Juillet 2023 à Février 2024
Led IP Market Research analysis, bringing over 400 key clients and proposing complete portfolio of products.
Aligned new offerings with existing portfolio, maximizing market impact
Developed innovative product strategies, leveraging technical expertise.
Principal ic design engineer / design lead
Qorvo , Toulouse - CDI (Contrat à Durée Indéterminée)
De Mars 2008 à Octobre 2022
At Qorvo, I contributed to power management advancements in the mobile phone market, focusing on cutting-edge integrated circuit development.
- Buffers Integrated Circuits for Envelope Tracking – Led design efforts, including analog design, simulations, and layout supervision.
- Envelope Tracking Integrated Circuits – Specialized in analog design (bandgap, LDO regulator, charge pump controller, protections, amplifier), mixed-signal simulations, layout supervision, and lab evaluation.
- SOI RF Switches – Designed analog controllers (bandgap, LDO regulator, switch driver, charge pumps), overseeing layout, lab evaluations, and test supervision.
Senior design engineer
Atmel , Rousset - CDI (Contrat à Durée Indéterminée)
De Septembre 2004 à Février 2008
Smartcard Market
• Specialized in non-volatile memory design, ensuring reliability and efficiency
• Conducted full custom design and mixed-signal simulations to optimize circuit performance
• Developed Verilog models for accurate representation and functional verification
• Implemented automation for Verilog model generation, streamlining design workflows and improving efficiency
Flash memory circuit & digital design engineer
Atmel , East kilbride - CDI (Contrat à Durée Indéterminée)
De Septembre 2002 à Septembre 2004
Computer Market
• Conducted full custom design and mixed-signal simulations for flash memory circuits
• Led digital design, including RTL development, synthesis, place & route, timing analysis, DRC & LVS
• Designed and optimized Low Pin Count / Firmware Hub interfaces for seamless integration
Microelectronics specialist and consultant.
Altran Technologies UK (now part of Capgemini) , Londres
De Août 2000 à Septembre 2002
Audio-video market
• Focused on back-end digital design, including Floorplanning, Place & Route, IPO, Physical Verification, and Timing Analysis
• Provided strategic support to a major IDM customer, ensuring optimized design implementation and process efficiency
• Contributed to EDA tool selection and flow automation, improving design workflows and maximizing performance
Formation complémentaire
Ingénieur
Institut National Polytechnique de Grenoble/PHELMA/ENSERG - IC design
1997 à 2000
Associations
Parcours officiels
Langues
Anglais - Courant
Espagnol - Notions
Français - Langue maternelle
Japonais - Notions